1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to the structure of a bipolar transistor usable in a high frequency analog field.
2. Description of the Prior Art
Recently, the operation speed of LSIs has been increased markedly. However, a further improvement in the operation speed of analog LSIs has been still required in the field of not only digital systems represented by large scale computers but also mobile communications systems, etc. As the semiconductor elements for constructing the analog LSIs, in general, silicon bipolar transistors are now widely used owing to the excellent linearity and the mass productivity.
When the analog LSIs are designed, the design factors such as cut-off frequency f.sub.T, maximum operating frequency f.sub.max early voltage V.sub.A, etc. of the bipolar transistor must be considered as the indices of the high speed performance of the analog LSIs. Conventionally, however, in order to improve the high speed performance of the bipolar transistor with priority, there exists such a tendency that the maximum operating frequency f.sub.max has been improved by increasing the cut-off frequency f.sub.T as high as possible at the sacrifice of the early voltage V.sub.A.
Therefore, conventionally, in order to increase the cut-off frequency f.sub.T of the bipolar transistor, the low-temperature epitaxial technique has been adopted to form a thin epitaxial base layer thereof, as shown in FIG. 18. FIG. 19 shows the characteristics of the cut-off frequency f.sub.T and the maximum operating frequency f.sub.max (ordinate) with respect to the collector current I.sub.C (abscissa) of the bipolar transistor manufactured as described above. FIG. 19 indicates that although the maximum value of the cut-off frequency f.sub.T can be increased as high as 44.3 GHz and further the maximum operating frequency f.sub.max can be also improved as high as 25.1 GHz, the early voltage V.sub.A is as low as 25 V.
In order to realize high frequency analog circuits, however, it is required that the maximum operating frequency f.sub.max and the early voltage V.sub.A are both high.
In more detail, as understood by the dependency of power gain upon frequency in the analog circuit shown in FIG. 20, for instance, the maximum operating frequency f.sub.max of the high frequency analog circuit is determined as a frequency at which the power gain (referred to as power amplification factor) becomes 1! or 0 dB!. Further, in the field of the analog circuits, the highest gain is required for amplifiers. However, when the power gain exceeds 20 dB greatly, since the probability of parasitic oscillation increases, the power gain is set to about 20 dB in general. Therefore, as understood by the graphical representation shown in FIG. 20, the operating frequency of the analog circuit is usually set to about 1/10 of the maximum operating frequency f.sub.max. In other words, when the operating frequency of the analog circuits is decided on the basis of the design specifications, about ten times of the operating frequency is needed as the maximum operating frequency f.sub.max thereof.
On the other hand, the relationship between the early voltage V.sub.A and the supply voltage V.sub.CC is as follows:
Although various current source circuits are used for the bipolar ICs, the basic current source circuit results in a circuit as shown in FIG. 21, in which I.sub.ref to I.sub.C0 is a reference current. In FIG. 21, a current I.sub.C1 the same as the reference current I.sub.C0 is supplied through a circuit of a transistor Q.sub.1, whose structure is the same as a transistor Q.sub.0. In the same way, a current I.sub.Cn n-times larger than the reference current I.sub.C0 is supplied through a circuit in which n-units of transistors (each structure is the same as the transistor Q.sub.0) are connected in parallel to each other.
Here, the bipolar transistor is provided with an early effect, so that the collector current I.sub.C can be expressed as EQU I.sub.C =I.sub.S .multidot.(1+V.sub.CE /V.sub.A).multidot.exp(V.sub.BE /V.sub.T)
where I.sub.S denotes a constant indicative of the transfer characteristics in the forward active region of the transistor; V.sub.CE denotes the collector-emitter voltage of the transistor; and V.sub.BE denotes the base-emitter voltage of the transistor. Further, V.sub.T can be expressed as V.sub.T =k. T/q where k denotes a Boltzmann's constant, T denotes the absolute temperature of the transistor and q denotes the charge elementary quantity.
Consequently, the currents I.sub.Cn and I.sub.C0 flowing through the transistors Q.sub.n and Q.sub.0, respectively can be expressed as EQU I.sub.Cn =n.multidot.I.sub.S .multidot.(1+V.sub.CEn /V.sub.A).multidot.exp(V.sub.BE /V.sub.T) EQU I.sub.CO =I.sub.S .multidot.(1+V.sub.CEO /V.sub.A).multidot.exp(V.sub.BE /V.sub.T)
Therefore, the ratio of I.sub.Cn /I.sub.C0 is not an ideal value of n times but as EQU I.sub.Cn /I.sub.Co =n(1+V.sub.CEn /V.sub.A)/(1+V.sub.CE0 /V.sub.A)
By the way, when considering the degree at which the above-mentioned non-ideal state can be allowed, it is necessary to avoid at least such a state that (n+1)-time current flows when n-units of the transistors are connected in parallel. This is because it is impossible to control the transistor currents on the basis of the number of the transistors. On the other hand, since the number n of the transistors for constructing an ideal circuit is about n=20, it will be preferable to satisfy the following conditions: EQU 20.multidot.(1+V.sub.CEn /V.sub.A)/(1+V.sub.CE0 /V.sub.A).ltoreq.21
or EQU (1+V.sub.CEn /V.sub.A)/(1+V.sub.CE0 /V.sub.A).ltoreq.1.05
Here, since the collector-base voltage V.sub.BC is zero, V.sub.CE0 =V.sub.BE to 1, and further since V.sub.CEn is roughly the same as the supply voltage V.sub.CC, the above-mentioned conditional expression can be expressed as EQU (1+V.sub.CC /V.sub.A)/(1+1/V.sub.A).ltoreq.1.05
Therefore, the following expression can be obtained: EQU V.sub.A .gtoreq.20.multidot.V.sub.CC -21
As a result, when the supply voltage V.sub.CC is 3V, the early voltage V.sub.A as high as 39 V is required. In the conventional transistors, however, even if the thickness of the base layer is reduced with the use of the low-temperature epitaxial technique, since the early voltage V.sub.A is as low as 25 V, there exists a problem in that it is impossible to obtain a necessary early voltage V.sub.A.